1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a split gate flash memory cell and a manufacturing method thereof.
2. Description of Related Art
A flash memory device provides the property of multiple entries, retrievals and erasures of data. Moreover, the stored information is retained even electrical power is interrupted. As a result, a non-volatile memory device is widely used in personal computers and electronic systems.
A typical flash memory device employs doped polysilicon to fabricate the floating gate and the control gate. Further, a dielectric layer is used to isolate the floating gate from the control gate, whereas the floating gate and the substrate are isolated from each other by a tunneling oxide layer. When a flash memory device performs the write/erase operation of information, proper biases are applied to the control gate and the source/drain regions to inject electrons into or to discharge electrons from the floating gate. Further, the reading of information from a flash memory device is achieved by applying a working voltage to the control gate. The conductive state of the floating gate influences the opening/closing of the channel, wherein the opening/closing of the channel can be interpreted as the binary value of either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
During the erasure of information of the above flash memory device, the amount of electrons being discharged is difficult to control. Therefore, over-erase is resulted when an excessive amount of the electrons or positive charges are discharged from the floating gate. When the over-erase phenomenon is serious, a channel current flow is induced under the floating gate even no working voltage is applied to the control gate, leading to an erroneous interpretation of the data.
To resolve the over-erase problem, a split gate flash memory device is introduced by the industry. FIG. 1 is a schematic, cross-sectional view of a split gate flash memory according to the prior art. As shown in FIG. 1, the flash memory cell includes, sequentially from the substrate 100, a tunneling dielectric layer 102, a floating gate 104, an inter-gate dielectric layer 106 and a selective gate electrode 108. The selective gate electrode 108 is configured above and at the periphery of the floating gate 104, wherein a portion of the selective gate 108 extends over a part of the substrate 100. The selective gate electrode 108 and the floating gate 104 are isolated from each other by a selective gate dielectric layer 110. The source region 112 is configured in the substrate 100 at one side of the floating gate 104, while the drain region 114 is disposed in the substrate 100 and is extended from one side of the selective gate electrode 108. Therefore, even when an over-erase phenomenon is serious, in which the channel under the floating gate 104 remains open when no working voltage is applied to the selective gate electrode 108, the channel under the selective gate electrode 108 still remains close to preclude a current flow between the drain region 114 and the source region 112 and to obviate an erroneous interpretation of the data.
A split gate structure, on the other hand, demands a larger split gate region and a larger memory cell dimension. The dimension of a split gate memory cell is thus larger than the dimension of the memory cell with the stack gate structure. Increasing the integration of devices thereby becomes difficult.
The increase of integration of integrated circuits by the miniaturization of device is achieved by reducing the gate length of a memory device. However, as the gate length is being reduced, the underlying channel length is also reduced. During the programming of such a memory cell, abnormal punch through thus easily occurs between the source region and the drain region, adversely affecting the electrical performance of the memory device.
Further, during the fabrication of the above flash memory device, there is a mask alignment problem in forming the selective gate electrode. The channel, which underlies the part of the selective gate electrode that extends over the substrate, can not be accurately defined. In other words, if misalignment occurs during patterning of the selective gate electrode, the channel lengths of two neighboring memory cells that share a common source region are not consistent. Asymmetric programming of the memory cells is thereby resulted, leading to different characteristics of two memory cells.
Accordingly, the present invention provides a split gate flash memory cell and a fabrication method thereof, wherein the punch through phenomenon generated at the source region and the drain region during the programming operation can be prevented to increase the effectiveness of a memory cell.
The present invention further provides a split gate flash memory cell and a fabrication method thereof, wherein a self-alignment process is used to form the selective gate electrode to prevent the problem of inconsistent channel lengths between two memory cells, and thereby obviating the problem of asymmetric programming of memory cells to increase the effectiveness of the memory cell.
The present invention also provides a split gate flash memory cell and a fabrication method thereof, wherein the selective gate is formed over a sidewall of floating gate and is extended from the floating gate sidewall to the trench sidewall in the substrate. The dimension of the memory cell can be reduced to increase the integration of the memory device.
The present invention provides a split gate flash memory cell, wherein the split gate flash memory cell is formed with a substrate, a stack structure, a first inter-gate dielectric layer, a second inter-gate dielectric layer, a selective gate electrode, a selective gate electrode dielectric layer, a source region and a drain region. The substrate further includes a trench. The stack structure is disposed on the substrate, and the stack structure includes, sequentially from the substrate, a tunneling dielectric layer, a floating gate and a cap layer. The first inter-gate dielectric layer is disposed on the sidewall at the first side of the stack structure, wherein the first inter-gate dielectric layer is contiguous to the top part of the trench. The second inter-gate dielectric layer is disposed on the sidewall at the second side of the stack structure. The selective gate electrode is configured on the sidewalls of first side of the stack structure and the trench. The source region is configured in the substrate beside the second side of the stack structure, while the drain region is configured at the bottom of the trench beside one side of the selective gate electrode.
The selective gate electrode of the split gate flash memory cell of the present invention is disposed on the sidewalls of the trench and of the first side of the stack structure. The channel region is thereby configured along the sidewall of the trench in the substrate (a vertical channel), wherein the channel length is determined by the depth of the trench. Therefore, even the device dimension (gate length) is reduced, the channel length can be accurately controlled by controlling the trench depth. The problem of a current flow between the source region and the drain region after the programming operation can be prevented. Further, the integration of the device can also increase.
The present invention further provides a fabrication method for a split gate flash memory device, wherein the method provides a substrate having a stack structure already formed thereon. Further, the stack structure includes a tunneling dielectric layer, a floating gate and a cap layer, sequentially from the substrate. After forming a source region in the substrate beside a first side of the stack structure, an inter-gate dielectric layer is formed on the sidewall of the stack structure. Thereafter, a trench is formed in the substrate beside a second side of the stack structure. Subsequent to the formation of a selective gate on the sidewall at the second side of the stack gate and on the sidewall of the trench, a drain region is formed at the bottom of the trench beside one side of the selective gate.
In accordance to the fabrication method for a split gate flash memory cell of the present invention, the selective gate is formed by a self-alignment method and not by a photolithography technique. The process window is increased, and the processing time and cost are scaled down. Moreover, the problems of inconsistent channel lengths between neighboring memory cells and asymmetric programming of memory cells are prevented to increase the reliability of the memory device.
Further, the selective gate is formed on the sidewalls of the stack structure and the trench, the channel region of the selective gate is configured in the substrate along the sidewall of the trench (vertical channel region). Therefore, even the device dimension (gate length) is reduced, the channel length is accurately controlled by controlling the depth of the trench. The problem of a current flow between the source region and the drain region after programming is prevented. Further, the integration of device can also increase.
The present invention further provides a fabrication method for a split gate flash memory device, wherein the method includes forming a tunneling dielectric layer, a first conductive layer and a mask layer sequentially on a substrate. A patterned mask layer is formed to expose a portion of the first conductive layer, and a cap layer is formed on the exposed first conductive layer. Thereafter, the mask layer is removed. Further using the cap layer as a mask, the first conductive layer and the tunneling dielectric layer are etched to form a stack structure. A source region is formed in the substrate beside a first side of the stack structure. An inter-gate dielectric layer is formed on the sidewall of the stack structure. Thereafter, a trench is formed in the substrate beside the second side of the stack structure. A selective gate dielectric layer is formed on the sidewall and at the bottom of the trench, and a second conductive layer is formed over the substrate. A portion of the second conductive layer is removed to form a conductive spacer on the sidewall at the first side of the stack structure, and a selective gate on the sidewall at the trench and the sidewall at the second side of the stack structure. A drain region is then formed at the bottom of the trench at one side of the selective gate.
In accordance to the fabrication method for a split gate flash memory cell of the present invention, after removing a portion of the conductive layer to form a conductive spacer on the sidewall at the first side of the stack structure, and a selective gate on the sidewall at the second side of the stack structure and the sidwall of the trench, and forming the drain region further includes performing an etching step to remove the conductive spacer.
Further, in accordance to the fabrication method for a split gate flash memory cell of the present invention, the selective gate is formed by a self-alignment method and not by a photolithography technique. The process window is thus increased, and the processing time and cost are reduced. Moreover, the problems of inconsistent channel lengths between neighboring memory cells and asymmetrical programming of memory cells are prevented to increase the reliability of the memory device.
Further, the selective gate is formed on the sidewalls of the stack structure and the trench, the channel region of the selected gate is configured in the substrate along the sidewall of the trench (vertical channel region). Therefore, even the device dimension (gate length) is reduced, the channel length is accurately controlled by controlling the depth of the trench. The problem of a current flow between the source region and the drain region after programming is prevented. Further, the integration of device can also increase.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.